There is a current interest in CMOS active pixel imagers for possible use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. The FIG. 1 circuit 100 exemplary pixel cell 150 is a 3T APS, where the 3T is commonly used in the art to designate use of three transistors to operate the pixel. A 3T pixel has a photodiode 162, a reset transistor 184, a source follower transistor 186, and a row select transistor 188. It should be understood that FIG. 1 shows the circuitry for operation of a single pixel, and that in practical use there will be an M times N array of identical pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodiode 162 converts incident photons to electrons which collect at node A. A source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at Node A. When a particular row containing cell 150 is selected by a row selection transistor 188, the signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 184 to node A. The gate of reset transistor 184 is coupled to a reset control line 190 which serves to control the reset operation in which Vrst is connected to node A. The row select control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source following transistor 186 and its output is selectively coupled to a column line 170 through row select transistor 188. Although not shown in FIG. 1, column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate of row select transistor 188 is coupled to row select control line 160.
As know in the art, a value is read from pixel 150 in a two step process. During a charge integration period the photodiode 162 converts photons to electrons which collect at the node A. The charges at node A are amplified by source follower transistor 186 and selectively passed to column line 170 by row access transistor 188. During a reset period, node A is reset by turning on reset transistor 184 and the reset voltage is applied to node A and read out to column line 170 by the source follower transistor 186 through the activated row select transistor 188. As a result, the two different values—the reset voltage and the image signal voltage—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column fines 170 and stored in sample and hold circuits. Then the column circuitry in the sample and hold circuits are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines.
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes an array of pixels 230 and a controller 232 which provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on the column lines 170 (FIG. 1) to a readout circuit 242 in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit 244. Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of the readout circuit 242.
FIG. 3 more clearly shows the rows and columns 349 of pixels 350. Each column includes multiple rows of pixels 350. Signals from the pixels 350 in a particular column can be read out to a readout circuit 352 associated with that column. The read out circuit 352 includes sample and hold circuitry for acquiring the pixel reset and integrated charge signals. Signals stored in the readout circuits 352 then can be read sequentially column-by-column to an output stage 354 which is common to the entire array of pixels 330. The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals are each supplied to the analog-to-digital converter.
FIG. 4 more clearly shows the column readout circuit 352 includes the sample and hold read out circuit in the prior art. The sample and hold circuit 400 is capable of sampling and holding two signals for subsequent subtraction. For example, a reset signal would be stored on capacitor 418 and the charge accumulated photo signal would be stored on capacitor 420. A downstream circuit subtracts these signals and outputs a signal to a digital to analog converter.
The capacitors 418, 420 are typically clamped to a clamping voltage on their back sides by switch 415 before a sampling operation. To store the pixel image signal on capacitor 420, a pulse signal is applied which temporarily closes the SHS switch 412 and couples the pixel with the front side of capacitor 420 through the column line 402. Thereafter, the SHS switch 412 is opened, which retains the charge accumulated signal in the capacitor 420 (assuming that Col. Select switch 428 is open). Similarly, to store the reset signal on capacitor 418, a pulse signal temporarily closes the SHS2 switch 410 and couples the pixel with the front side of capacitor 418 through the column line 402. Thereafter, the SHS2 switch 410 is opened, which retains the reset signal in the capacitor 418 (assuming that Col. Select switch 426 is open).
In order to read out the stored reset and charge accumulated signals from the capacitors 418, and 420 a pulse signal is applied closing a crowbar switch 413 and Col. Select switches 426 and 428 thereby forcing signals on capacitors 418, 420 into differential amplifier 434. Signals output from amplifier 434 are provided to downstream circuits. Although amplifier 434 is shown as processing the reset and image signals to provide differential signals to downstream circuits, amplifier 434 can also be arranged to subtract the signals and provide single ended signals to downstream processing circuits.
As fabrication techniques get better, an increasing number of digital processing circuits are being implemented on the same chip as an image sensor. This increases substrate noise coupling to a pixel, which can compromise the signal to noise ratio of the image sensor core. The substrate noise occurs when spurious noise signals are injected locally into the substrate through ohmic or capacitive coupling, thereby breaking the equipotentiality of the substrate.
In traditional CMOS APS devices the two signals, corresponding to the image signal level (Vsig) and the reset signal level (Vrst) are read out of each pixel at two different times. The Vsig and Vrst voltages stored on the respective capacitors 420, 418 with reference to the precharge clamping voltage Vclamp. Thus,Vsig=Vsig−Vclamp  (1)
where Vclamp is the clamping voltage. Likewise,Vrst=Vrst−Vclamp  (2)
During readout the difference between Vsig and Vrst voltages is generated as an output. Ideally, this will be:Vdiff=Vrst−Vsig  (3)
However, in practice there will be an uncorrelated noise component associated with Vclamp, giving an actual output voltage ofVdiff=Vrst−Vsig−(Vclamp(rst)−Vclamp(sig))  (4)
It would be desirable to have a column readout circuit that compensates for substrate and other common mode noise that is encountered during a pixel read out operation and eliminates the noise term.